A Introduction

Research and manufacturing related to silicon devices, circuits, and systems often relies on the wet-chemical etching of silicon wafers. The dissolution of silicon using liquid solutions is needed for deep etching and micromachining, shaping, and cleaning. Also, wet-chemistries are often used for defect delineation in single crystal silicon materials. In this paper, a review of the typical wet-chemical recipes used by engineers is given. As many sources as possible have been used to present a concise listing of etchants and processes.

B Wafer Cleaning

A sequence of chemistries is typically used to clean silicon wafers. This sequence was first developed at the RCA laboratories, and is therefore often referred to as the RCA process. This chemical sequence does not attack the silicon material, but selectively removes the organic and inorganic contamination that resides on the wafer surface. The following is a typical RCA process; many variations to the ordering of the sequence and chemical ratios are used throughout the industry.

• General Clean: A general cleaning is accomplished by using a mixture of Sulfuric Acid and Hydrogen Peroxide. Mixing these chemicals is dangerous and generates extreme heat. This industry standard clean removes organic and inorganic contamination from the wafer. 2-10 minute clean is recommended. Strong rinse in DI water is required after this cleaning step.
• Particle Removal: A Megasonic clean (at about 70 C) in a 5:1:1 ratio mixture of DI water: Ammonium Hydroxide : Hydrogen Peroxide will remove silica and silicon particles from the wafer, as well as remove certain organic and metal surface contamination. 2-10 minute clean is recommended. Strong rinse in DI water is required after this cleaning step.
• Oxide Removal: A 15-60 second dip in 1:20 HF:DI water will remove the native oxide layer and any contamination in the oxide from the wafer surface. HF is extremely dangerous and must be handled with great care. Strong rinse in DI water is required after this cleaning step.
• Metal Contamination Removal: A Megasonic clean (at about 70 C) in a 6:1:1 ratio mixture of DI water: HCL : Hydrogen Peroxide will remove certain ionic and metal surface contamination. 2-10 minute clean is recommended. Strong rinse in DI water is required after this cleaning step.
• Spin Rinse Dry: Wafers should be rinsed and dried in a standard spin-rinse dryer.

Megasonic agitation is commonly used with the chemical bath and most commonly with the particle removal step. Also, heavy DI rinse steps are used between each chemical treatment. DI rinsing may use dump-baths, over-flow baths, and spray-dump baths, as well as combinations. Proper removal of all cleaning chemistry with 18MegaOhm DI water is critical and needed after each chemical bath. Any text book on the topic of semiconductor or silicon processing is an excellent resource for further information regarding the RCA cleaning process ( for example see S.Wolf and R. Tauber, Silicon Processing:Vol.1, Lattice Press, CA, 1986). There are commercially available premixed cleaning solutions that can be used directly to clean wafers and serve the same purpose of the RCA cleaning process. These chemicals typically achieve the function of several cleaning steps with one solution (see for example JT Baker, Baker Clean Solution).

C Anisotropic KOH Etching

KOH is one the most commonly used silicon etch chemistry for micromachining silicon wafers.

1. Anisotropic KOH Etching Rates vs. Orientation

The KOH etch rate is strongly effected by the crystallographic orientation of the silicon (anisotropic). Table 1 relates silicon orientation-dependent etch rates (µm min-1) of KOH to crystal orientation with an etching temperature of 70°C. Table 1 is taken directly from [1]. In parentheses are normalized values relative to (110).

The (110) plane is the fastest etching primary surface. The ideal (110) surface has a more corrugated atomic structure than the (100) and (111) primary surfaces. The (111) plane is an extremely slow etching plane that is tightly packed, has a single dangling-bond per atom, and is overall atomically flat. As shown above, the strongly stepped and vicinal surfaces to the primary planes are typically fast etching surfaces.

2. KOH Etching Rates vs. Composition and Temperature

Table 2 relates silicon orientation-dependent etch rates of KOH to percent composition, temperature, and orientation. Table 2 is taken directly from [2]. As with all wet-chemical etching solutions, the dissolution rate is a strong function of temperature. Significantly faster etch rates at higher temperatures are typical, but less ideal etch behavior is also common with more aggressive etch rates. Also, heavy boron doping can significantly harden the silicon and sharply reduce the etch rate.

D Anisotropic TMAH (tetramethylammonium hydroxide) Etching

Similar to KOH etching, TMAH is commonly used for fast removal and silicon micromachining.

1. TMAH Etching Rates vs. Orientation

The orientation dependence of the TMAH etch rate is similar to KOH and varies similarly in accordance to the atomic organization of the crystallographic plane. Table 3 relates silicon orientation-dependent etch rates of TMAH (20.0wt%, 79.8°C) to orientation. Table 3 is taken directly from [6].

2. TMAH Etching Rates vs. Composition and Temperature

Similar to KOH, the TMAH etch rate varies exponentially with temperature. Table 4 relates silicon orientation-dependent etch rates of TMAH to percent composition, temperature, and orientation. Table 4 is taken directly from [2].

E EDP

Similar to KOH, EDP is often used for fast removal and silicon micromachining. Table 5 relates silicon orientation-dependent etch rates in EDP solutions to Temperature and Orientation.

F Isotropic Silicon Etches

Often, isotropic etchants having dissolution rates independent of orientation are needed. These chemical mixtures tend to uniformly remove material, and are limited by the mass transport of chemical species to the crystal surface. The actual surface reaction rates are so great that variations to atomic structure do not alter the reaction speed relative to chemical transport. Table 6 lists several common recipes and is taken directly from [14].

G Silicon Defect Delineation Etches

Certain chemical etchants are strongly dependent on defects, and defect structures in the single crystal silicon. These etchants are commonly used to high-light or delineate defects in the material. Table 7 lists the most common defect delineation mixtures, and is taken directly from [14]

H Conclusion

There are many wet-chemical etch recipes known for etching silicon. These processes are used for a variety of applications including micromachining, cleaning, and defect delineation. The detailed behaviour and rate of the etchant will vary between laboratory environments and exact processes. However, the data and phenomena recorded above have been reported by many researchers and manufacturers. For further details the reader is encourage to fully explore the direct and indirect references cited.

I References

[1] K. Sato et al.[Characterization of orientation-dependent ethcing properties of single-crystal silicon: effects of KOH concetration (Sensors and Actuators A 64 (1988) 87-93)]

[2] R. Hull [ Properties of Crystalline Silicon (INSPEC, London, 1999)]

[3] H. Seidel, L. Cseprege, A. Heuberger, H. Baumgarel [ J. Electrochem. Soc. (USA) vol. 137 (1990) p. 3626-32]

[4] D.L. Kendall [Annu. Rev. Mater. Sci (USA) vol.9 (1979) p.373]

[5] J.B. Price [Semiconductor Silicon 1973 Eds. H.R. Huff, R.R. Burgess (E;

[6] M. Shikida, K. Sato, K. Tokoro, D. Uchikawa [Dept. of Micro Sysytems Engineering, Nagoya University, Japan]

[7] O. Tabata, R. Asahi, H. Funabashi, K. Shimaoka, S. Sugiyama [Sens. Actuators A (Switzerland) vol. 34 (1992) p.51-7]

[8] U. Schnakenberg, W. Benecke, P. Lange [Proc. 1991 Int. Conf. Solid-State Sensors and Actuators (Tansducers 91) San Fransisco, USA, 1991 (IEEE, New York, NY, 1991) p.815-8]

[9] M. Sekimura [ Proc. 12th IEEE Int. Micro-Electrical Mechanical Systems Conf. (MEMS 1999), Orlando, Florida, USA, p.650-5]

[10] R.M. Finne, D.L. Klein [J. ElectroChem. Soc. (USA) vol. 114 (1967) p.965-70]

[11] A. Reisman, M. Berkenbilt, S.A. Chan, F.B. Kaufman, D.C. Green [J. ElectroChem Soc. (USA) vol. 126 (1979) p.1406-14]

[12] E. Bassous [IEEE Trans. Electron Devices (USA) vol.ED-25 (1978) p.1178]

[13] G. Kaminsky [J. Vac. Sci. Technol. B (USA) vol.3(1985) p.1015]

[14] S. Walsh[ Wetch Etching fo Semiconductor Fabrication, Janus Ventures Inc.]

[15] B. Schwartz, H. Robbins [J. ElectroChem Soc. 10B, 365 (1961)]

[16] A. Stoller, R. Speers, S Opresko [ RCA Rev 31, 265 (1970)]

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[18] M. Theunissen, J. Apples, W Verkuylen [J. ElectroChem Soc 117, 959 (1970)]

[19] W. Hoffmeister int. [J. Appl Radiat Isot 2, 139 (1969)]

[20] S. Ghandi [ VLSI Fabrication Principles , Wiley InterScience (1983)]

[21] K. Ravi [ Imperfections and impurities in Semiconductor Silicon, Wiley (1981)]

[22] T. Mills, E. Sponheimer [ Precision VLSI Cross Sectioning and Staining 1982 IEEE Proceedings]

[23] D. Elliot [ Integrated Circuit Fabrication Technology, McGraw-Hill (1982)]

[24] Semi Spec Identification of Structures and Contaminents seen on Specular Silicon Surfaces ASTM

[25] M. Jacques, [The Chemistry of Failure Analysis, IEEE EDM (1979)]

[26] J. Heiss Jr., J. Wylie, U.S. Patent 4,089,704 (1978)

[27] T. Chu, R. Keim Jr.[ J. ElectroChem Soc. 122, 995 (1975)

January 2003
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